In designing a digital logic gate in a semiconductor integrated circuit, an important objective is to reduce the gate propagation delay. This is the average time needed for an output signal of the gate to switch from a desired logical low or "0" value to a desired logical high or "1" value and vice versa in response to a corresponding change in an input signal to the gate. Such a gate typically consists of a switching transistor in combination with a mechanism to pull the output signal rapidly down to logical "0" and/or a mechanism to pull the output signal rapidly up to logical "1".
Referring to the drawings, FIG. 1 illustrates a conventional inverting logic gate of the type briefly mentioned by H. Ishino in U.S. Pat. No. 4,107,547. This transistor-transistor logic (TTL) inverter receives an input voltage V.sub.IN at the base of a bipolar NPN transistor QA and provides an output voltage V.sub.OUT at the collector of another bipolar NPN transistor QB having its emitter grounded and its base connected to the emitter of transistor QA. The collector of transistor QA is resistively coupled to a voltage/current source V.sub.CC and is coupled through a conventional PN diode DD to the collector of transistor QB.
Transistor QA or QB is in the on or conductive state when its base-to-emitter junction voltage V.sub.BEQA or V.sub.BEQB equals a PN diode-drop voltage termed a "V.sub.BE " and is in the off or substantially non-conductive state when voltage V.sub.BEQA or V.sub.BEQB is less than 1 V.sub.BE. Accordingly, transistors QA and QB both turn on as input voltage V.sub.IN is raised from a logical "0" of less than 1 V.sub.BE to a logical "1" of 2 V.sub.BE. Both transistors QA and QB go into "deep" saturation. This means that the base-collector junction of transistor QA or QB is sufficiently forward biased so as to be fully conductive. As transistor QB saturates, it draws progressively more current from source V.sub.CC to actively pull output voltage V.sub.OUT down to a logical "0" near 0 volt. When voltage V.sub.IN is brought back down to its logical "0", transistors QA and QB both turn off. Depending on the load which voltage V.sub.OUT is applied to, diode DD may be conductive. If so, a PN diode-drop voltage of 1 V.sub.BE occurs across diode DD, and voltage V.sub.OUT rises up to a logical "1" of at least 1 V.sub.BE below V.sub.CC.
A significant drawback of this inverter is that there is relatively large output voltage swing since transistor QB turns off when voltage V.sub.OUT rises to logical "1". This voltage swing limits the output switching speed. Another disadvantage is that transistors QA and QB are initially both in deep saturation as voltage V.sub.IN is switched from logical "1" to logical "0", and their bases therefore contain large amounts of stored charge. In transistors not made by gold-doped processes, these charges take relatively large amounts of time to flow to ground compared to the input switching time. As a result, the low-to-high output switching time is limited by the time needed to discharge transistors QA and QB from deep saturation. Even with gold-doped transistors, the average propogation delay is usually about 3 nanoseconds.
Another conventional inverter as disclosed by J. Kane et al. in U.S. Pat. No. 3,962,590 is shown in FIG. 2. This TTL inverter contains all of the elements of FIG. 1 plus an NPN bipolar transistor QC having its collector connected to source V.sub.CC and its base and emitter coupled, respectively, between the collector of transistor QA and the anode of diode DD. A Schottky diode DA connected between the base and collector of transistor QA Schottky clamps it. Transistor QB is similarly Schottky clamped with a Schottky diode DB.
Although Kane et al. do not describe the switching operation of this inverter in detail, I understand it to operate as follows: As voltage V.sub.In is raised to a logical "1" of 2 V.sub.BE, transistors QA and QB both turn on and saturate. Because they are Schottky clamped, neither normally goes into deep saturation. Instead, both go into "low" saturation where their base-collector junctions are forward biased, but below the normal fully conductive level. This occurs because diodes DA and DB become conductive and clamp the voltages across the base-collector junctions of transistors QA and QB at a Schottky diode-drop voltage which may be termed as "V.sub.SH " and is normally slightly less than 1 V.sub.BE. This clamped value of 1 V.sub.SH is usually not high enough to allow either of these base-collector junctions to become fully conductive in the forward direction. As transistor QB turns on, it actively pulls voltage V.sub.OUT down. Meanwhile, transistor QC turns off. When voltage V.sub.In is brought back down to a logical "0" of 1 V.sub.BE or lower, transistors QA and QB turn off. Transistor QC turns on to actively pull voltage V.sub.OUT up to a logical "1" of at least 2 V.sub.BE below V.sub.CC if diode DD is conductive.
By having transistors QA and QB Schottky clamped, less charge must be dissipated from their bases as voltage V.sub.IN switches from logical "1" to logical "0". This reduces the low-to-high output switching time compared to that of FIG. 1. However, diode DA or DB may not always keep its transistor QA or QB from going into deep saturation. Because of processing variations from transistor to transistor and different doping levels in the collector and base compared to the emitter and base, the base-collector junction may become conductively forward biased at a voltage less than 1 V.sub.BE. Sometimes the base-collector junction becomes conductively forward biased at a voltage of 1 V.sub.SH or less. A Schottky-clamped transistor may also go into deep saturation if its Schottky diode is improperly designed or is operated at a high current level. Moreover, there is a relatively sharp bend in the curve of collector-to-emitter voltage as a function of collector current that defines the low and deep saturation regions. In short, a Schottky-clamped transistor may still accumulate a moderately large amount of charge. In addition, the output voltage swing is again relatively large since transistor QB turns off during switching operation. The average propagation delay for a gate such as that of FIG. 2 is usually about 2 nanoseconds.